Method for manufacturing single-crystal-silicon wafers

ABSTRACT

According to the present invention, there are provided a method for producing a silicon single crystal wafer which contains oxygen induced defects by subjecting a silicon single crystal wafer containing interstitial oxygen to a heat treatment wherein the heat treatment includes at least a step of performing a heat treatment using a resistance-heating type heat treatment furnace and a step of performing a heat treatment using a rapid heating and rapid cooling apparatus, and a silicon single crystal wafer produced by the method. There can be provided a method for producing a silicon single crystal wafer which has a DZ layer of higher quality compared with a conventional wafer in a wafer surface layer part and has oxygen induced defects at a sufficient density in a bulk part and the silicon single crystal wafer.

TECHNICAL FIELD

The present invention relates to a method for producing a silicon singlecrystal wafer which has a defect-free layer (DZ layer, Denuded Zone) ina surface layer part, and has sufficient gettering sites in a bulk part.

BACKGROUND ART

It is required for a silicon single crystal in the light ofcharacteristics of a device that a surface layer part which serves as anactive layer of device has no crystal defects. Furthermore, there isrequired a wafer (IG wafer) having a high intrinsic gettering (IG)effect which has gettering sites for heavy metal contamination in a bulkpart of the wafer, since there exists in a process for fabricating adevice a process wherein heavy metal contamination which degrades devicecharacteristics is easily caused.

As a method for forming oxide precipitates or crystal defects such asdislocations and stacking faults resulting from them (hereinafterreferred to as oxygen induced defects) in a wafer, there is known, forexample, a method wherein a CZ silicon single crystal wafer which isproduced by Czochralski (CZ) method and contains interstitial oxygens ata certain concentration is subjected to a multi-stage IG heat treatment(for example, a three stage heat treatment of high temperature, lowtemperature and medium temperature, or the like) to form a DZ layer inthe surface layer part and form oxygen induced defects in the bulk part.

However, if an IG wafer having high IG ability is produced according tosuch a method, there is a disadvantage that the oxygen induced defectstend to be increased also in the surface layer part used serving as adevice active layer. This is because, the IG ability is greatlydependent on the amount of oxide precipitates (a density of oxideprecipitates) in the wafer, and thus there has been employed as theeasiest method of improving it, a method in which concentration ofinterstitial oxygen contained in the silicon wafer to be subjected to IGheat treatment is increased, but at the same time increase of oxideprecipitates in a surface layer part of the wafer are also caused.Moreover, in the case that heat treatment is performed for a long timein order to induce crystal defects at a high density inside, oxygeninduced defects which exists inside are significantly grown with theprolonged heat treatment, which may reach the device active region insome cases.

Furthermore, as a grown-in defect formed in a CZ wafer during crystalgrowth according to Czochralski method, it is known that in addition toa minute oxide precipitates, a void type crystal defect (hereinafterreferred to as a void defect (referred to also as COP)) which isconsidered to be an agglomerations of vacancies is existed. And, it isknown that the void defects remain in a DZ layer of a conventional IGwafer. That is, even in a DZ layer (a defect-free layer), defectsactually eliminated (reduced) are the defects due to oxide precipitates,and such void defects are not reduced.

It has been required that the wafer having an excellent getteringability wherein no crystal defects exist in a region to a certain depthfrom a surface and sufficient gettering sites such as a oxideprecipitates exist in a region deeper than a certain depth is producedefficiently. The reason for needing the excellent gettering ability isthat the influence of a heavy metal impurity is one of the causes ofreducing the yield in a device process, and that insufficient formationof gettering sites such as oxide precipitates in a wafer causes shortageof gettering, and thus heavy metal is captured in the device activelayer to cause degradation of device characteristics such as increase ina leakage current.

Of course, the best way is to keep cleanliness in all the steps of adevice process, but it is actually impossible to prevent a wafercompletely from suffering from heavy metal contamination or the like.Therefore, it is desired that the oxygen induced defects serving asgettering sites are formed sufficiently inside a wafer. On the otherhand, as for the surface layer part serving as a device active layer, itis desired that the region having neither oxide precipitate nor crystaldefect such as a void defect exist to a sufficient depth.

DISCLOSURE OF THE INVENTION

The main object of the present invention is to provide a method forproducing a silicon single crystal wafer which has a DZ layer of higherquality compared with a conventional wafer in a wafer surface layer partand has oxygen induced defects at a sufficient density in a bulk part.

In order to achieve the above-mentioned object, a method for producing asilicon single crystal wafer of the present invention is a method forproducing a silicon single crystal wafer which contains oxygen induceddefects by subjecting a silicon single crystal wafer containinginterstitial oxygen to a heat treatment wherein the heat treatmentincludes at least a step of performing a heat treatment using aresistance-heating type heat treatment furnace and a step of performinga heat treatment using a rapid heating and rapid cooling apparatus.

As described above, according to the present invention, as aprecipitation heat treatment for forming gettering sites such as oxideprecipitates or the like in a bulk part and a heat treatment foreliminating void defects in the surface of a wafer, there are conductedboth a heat treatment using a resistance-heating type heat treatmentfurnace (it is a so-called batch processing furnace in which a treatmentof two or more wafers can be performed at the same time, generally thereare a vertical-type furnace and a horizontal-type furnace) and a heattreatment using a rapid heating and rapid cooling apparatus (it isusually a single wafer processing apparatus, and is a so-called RTA(Rapid Thermal Annealing) apparatus in which it is possible to increaseand decrease a temperature to the target temperature in several secondsto several tens of seconds, and a lamp heating type apparatus using aninfrared lamp is often employed). By combining the heat treatments bythese apparatuses, there can be achieved the effect that generation ofoxygen induced defects is promoted and the region where the void defectsare reduced (hereinafter occasionally referred to as a void-free region)is enlarged.

In that case, it is preferable that the heat treatment using theresistance-heating type heat treatment furnace is performed at 1000 to1300° C. for 10 to 300 minutes, and the heat treatment using the rapidheating and rapid cooling apparatus is performed at 1000 to 1350° C. for1 to 300 seconds.

This is the suitable range of the heat treatment conditions set for bothof the apparatuses used for the heat treatment of the present invention.If it is performed at a lower temperature for a shorter period than theaforementioned range, the effects of promoting oxygen induced defectsand enlarging the void-free region becomes insufficient. On thecontrary, if it is performed at a higher temperature for a longerperiod, cost may be increased for the reason that degradation of devicecharacteristics due to heavy metal contamination becomes remarkable, aproblem arises in a durability of the apparatus due to increase of loadon the apparatus, throughput is reduced and the like, and thus it is notpractical.

In this case, it is preferable to use as the silicon single crystalwafer to be subjected to the heat treatment, a silicon single crystalwafer which is doped with nitrogen at a concentration in the range of1×10¹⁰ to 5×10¹⁵ number/cm³.

If it is doped with nitrogen, although a density of grown-in defects isincreased, a size of them becomes small. Therefore, by performing theheat treatment, the grown-in defects in a surface layer part can beeliminated efficiently, and a high density of oxide precipitates can beobtained in a bulk part. If nitrogen concentration is lower than thelower limit, the above-mentioned effect of nitrogen doping can not befully achieved. If nitrogen concentration is higher than the upperlimit, formation of a single crystal is inhibited when the crystal isgrown

In addition, it is preferable to use the silicon single crystal waferwhich is doped with carbon at a concentration in the range of 0.1 to 5ppma as the silicon single crystal wafer to be subjected to the heattreatment.

As described above, oxygen precipitation can be promoted also by dopingwith carbon, and the concentration of 0.1 ppma or more is needed inorder to obtain the effect. If it is more than 5 ppma, formation of asingle crystal is inhibited when the single crystal is grown as in thecase of nitrogen doping.

According to the present invention, there is provided a silicon singlecrystal wafer having a defect-free layer in which there exist neitheroxygen induced defect nor crystal defect such as a void defect in asurface layer part, and having sufficient gettering sites in a bulk partwhich is produced by the above-mentioned production method.

According to the present invention, there can be produced a siliconsingle crystal wafer which has a DZ layer of a higher quality than theconventional wafer in a surface layer part of the wafer, contains asufficient density of oxide precipitates in a bulk part, and has a highgettering ability.

BRIEF EXPLANATION OF THE DRAWINGS

FIG. 1 is a schematic view showing one example of the rapid heating andrapid cooling apparatus (RTA apparatus) used in the present invention.

FIG. 2 is a graph showing a result of the relation between a polishingamount from the wafer surface and a TZDB good chip yield in Examples 3and 4 and Comparative Examples 5 and 6.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be explained in detail below.

The inventors of the present invention have studied further and madeexperiments in relation to production of a silicon single crystal waferwhich has a DZ layer in which there is no crystal defect in a surfacelayer part, and has a sufficient density of gettering sites, such asoxide precipitates in a bulk part. As a result, they have found that theabove-mentioned object can be achieved by performing a heat treatment intwo steps at least using a resistance-heating type heat treatmentfurnace and a rapid heating and rapid cooling apparatus. They have thenstudied the conditions therefor, and thereby have completed the presentinvention.

As described above, the heat treatment of the present invention needs tobe performed in two steps at least using the resistance-heating typeheat treatment furnace and the rapid heating and rapid coolingapparatus, and in regard to the heat treatment conditions of the heattreatment apparatuses, it has been found that the heat treatment may beconducted under the following heat treatment conditions depending ontypes of heat treatment apparatuses from results of various experiments.

The heat treatment using the resistance-heating type heat treatmentfurnace is preferably conducted at 1000-1300° C. for 10-300 minutes.Furthermore, in order to eliminate efficiently grown-in defects in thesurface layer part of the wafer under these conditions, the heattreatment is preferably conducted at 1100° C. or more for one hour ormore. For the heat treatment atmosphere, a hydrogen atmosphere, an inertgas atmosphere such as argon atmosphere and the like, or an atmosphereof a mixture of these gases is suitable.

Moreover, if oxidation heat treatment is performed continuously afterthis heat treatment, the inner wall oxide film of a void defect iseliminated by out-diffusion in the heat treatment at the former step,and then, void defects are eliminated efficiently by injecting of theinterstitial silicon in the subsequent oxidation, and thus a void-freeregion can be formed more deeply.

The heat treatment using the rapid heating and rapid cooling apparatus(RTA apparatus) is performed at 1000 to 1350° C. for 1 to 300 seconds.Thereby, the void defects near the most external surface of the wafer(referred to also as COP) can be removed efficiently, and at the sametime, the effect of increasing the internal oxygen induced defects canbe achieved. In order to achieve these effects further efficiently, theheat treatment at 1200° C. or more for about 30 to 60 seconds issuitable. Moreover, in order to increase oxygen induced defects,nitrogen atmosphere, oxygen atmosphere, or an atmosphere of a mixture ofthese gases, in which vacancies and interstitial silicon atoms areinjected is suitable for the heat treatment atmosphere.

The order of the heat treatment steps using these two kinds of heattreatment apparatuses is not limited specially. Moreover, it is alsopossible to repeat these heat treatment steps two or more times.However, taking into consideration a production cost of a silicon wafer,it is preferable to perform each step only one time. Moreover, the sameeffect can be achieved, even if these heat treatments are added during aprocess of fabricating a device, or performed also as the heat treatmentin the process of fabricating a device.

On the other hand, it is necessary that the wafer used in the presentinvention (the wafer to be subjected to heat treatment) is a siliconsingle crystal wafer which contains interstitial oxygen in such anamount that oxide precipitates can be formed in a bulk part after theheat treatment. If it is a usual CZ wafer or a so-called MCZ wafer whichis pulled with applying a magnetic field thereto, several ppma to 30ppma (JEIDA (Japan Electronic Industry Development Association)standard) of interstitial oxygen can be contained. However, in order toobtain the oxide precipitates at a sufficient density after the heattreatment, 15 to 25 ppma is preferable.

Moreover, it is suitable to use the silicon single crystal wafer whichis doped with nitrogen and carbon, since there can be achieved effectssuch as of promoting oxygen precipitation, and of making a size of agrown-in defect small to be eliminated easily by the heat treatment.

As for nitrogen concentration, it is preferable to use a silicon singlecrystal wafer which is doped with nitrogen in the concentration range of1×10¹⁰ to 5×10¹⁵ number/cm³. If it is doped with nitrogen, although adensity of a grown-in defect is increased, a size thereof becomes small.Accordingly, when the heat treatment is performed, the grown-in defectsin a surface layer part can be efficiently eliminated, and a highdensity of oxide precipitates can be obtained in a bulk part. If thenitrogen concentration is less than 1×10¹⁰ number/cm³ which is a lowerlimit, the above-mentioned effect by nitrogen doping can not be obtainedsufficiently. If it is higher than 5×10¹⁵ number/cm³ which is an upperlimit, formation of single crystal is inhibited at the time of growth ofcrystal, and therefore it is not desirable.

On the other hand, as for carbon concentration, it is preferable to usethe silicon single crystal wafer which is doped with carbon in the rangeof 0.1 to 5 ppma. Oxygen precipitation can be promoted also by dopingwith carbon, and the concentration of 0.1 ppma or more is necessary inorder to achieve the effect. If it is higher than 5 ppma, formation ofsingle crystal is inhibited at the time of growth of a single crystal,as in the case of nitrogen doping, and therefore it is not desirable.

In order to produce the silicon single crystal wafer which is doped withnitrogen or carbon at a predetermined concentration, there can be used amethod, such as a method of charging a predetermined amount of thesilicon wafer with a nitride film into a quartz crucible for melting araw material silicon, bringing a carbon rod into contact with thesilicon melt in a predetermined area for predetermined time, or thelike, when the usual CZ single crystal is pulled. And, theconcentrations can be controlled suitably by calculating taking intoconsideration a segregation coefficient of each element.

The resistance-heating type heat treatment furnace for the siliconsingle crystal wafer used in the present invention is a so-called batchprocessing furnace in which a treatment of two or more wafers can beperformed at a time, and generally there are a vertical-type furnace anda horizontal-type furnace. An example of a horizontal type batchprocessing furnace may include an apparatus such as UL-260-10Hmanufactured by Tokyo Electron Limited. They are furnaces used quitepopularly. In the present invention, the heat treatment can be conductedusing a furnace which has been used generally.

The rapid heating and rapid cooling apparatus is usually a single waferprocessing apparatus, and is a so-called RTA (Rapid Thermal Annealing)apparatus in which it is possible to increase and decrease a temperatureto an intended temperature in several seconds to about several tens ofseconds. Examples of them include an apparatus wherein the lamp heatingtype using the infrared lamp is employed. Moreover, an example of acommercially available apparatus may include an apparatus SHS-2800manufactured by Steag MicroTech International. They are neitherextraordinarily complicated nor expensive.

An example of the rapid heating and rapid cooling apparatus for thesilicon single crystal wafer used in the present invention will be shownbelow. FIG. 1 is a schematic view of a RTA apparatus.

The heat treatment apparatus 10 shown in FIG. 1 has a chamber 1 made ofquartz, and a wafer is subjected to heat treatment within this chamber1. Heating is performed by heating lamps 2 arranged so that a chamber 1may be surrounded from the directions of up, down, left and light. Theelectric power supplied to each of the lamps can be controlledindependently.

An automatic shutter 3 is provided at the gas exhausting side, and itshuts the outer air. The automatic shutter 3 has a wafer insertion portnot shown in the figure, which can be opened and closed by a gate valve.The automatic shutter 3 is also provided with a gas exhausting outlet,and thereby the atmosphere in the furnace can be controlled.

The wafer 8 is placed on a three-point supporting part 5 formed on aquartz tray 4. A buffer 6 made of quartz is provided at the gas inletside of the tray 4, and it can prevent the wafer from being directlyblown by the introduced gas flow.

Further, the chamber 1 is provided with a special window for temperaturemeasurement, which is not shown in the figure, and the temperature ofthe wafer 8 can be measured by a pyrometer 7 installed in the outside ofthe chamber 1 through the special window.

By using the heat treatment apparatus 10 mentioned above, the heattreatment for rapid heating and rapid cooling of wafer is performed asfollows.

First, the wafer 8 is loaded into the chamber 1 from the insertion portand placed on the tray 4 by a wafer handling apparatus, which isinstalled at a position adjacent to the heat treatment apparatus 10 butnot shown in the figure. Then, the automatic shutter 3 is closed.

The inside of the chamber 1 is sufficiently purged with nitrogen gas,and then the atmospheric gas is changed to hydrogen, argon or a mixedgas of nitrogen, oxygen and the like. Subsequently, electric power issupplied to the heating lamps 2 to heat the wafer 8 to a predeterminedtemperature, for example, 1000 to 1350° C. In this operation, it takes,for example, about 30 seconds to attain the desired temperature. Then,the wafer 8 is kept at the temperature for a predetermined period oftime, and thus the wafer 8 can be subjected to a high temperature heattreatment. When the predetermined time has passed and the hightemperature heat treatment was finished, output of the lamps is reducedto lower the temperature of the wafer. This temperature decrease canalso be attained during a period of, for example, about 30 seconds.Finally, the wafer is unloaded by the wafer handling apparatus to finishthe heat treatment.

When other wafers are further subjected to the heat treatment, thewafers can be successively loaded to continuously perform the RTAtreatment. When the thermal oxidation treatment is performed by using anRTA apparatus, the treatment temperature, treatment gas atmosphere andthe like can be changed.

The present invention will be explained concretely hereafter with theExamples of the present invention and Comparative Examples. However, thepresent invention is not limited to these.

EXAMPLE 1, EXAMPLE 2, COMPARATIVE EXAMPLES 1-4

The following two kinds of CZ silicon wafers (A, B) were produced, andthe following experiments were conducted using them.

Example 1: Wafer A: A diameter of 150 mm, a conductivity type of p type,crystal orientation of <100>, a resistivity of 10 Ω·cm, nitrogenconcentration of 1.0×10¹³ number/cm³ (a calculated value), oxygenconcentration of 15 ppma (JEIDA (Japan Electronic Industry DevelopmentAssociation) standard).

Example 2: Wafer B: A diameter of 150 mm, a conductivity type of p type,crystal orientation of <100>, a resistivity of 10 Ω·cm, non doping withnitrogen, oxygen concentration of 15 ppma (JEIDA).

First, these wafers were subjected to heat treatment with ahorizontal-type batch processing furnace (manufactured by Tokyo ElectronLimited, UL-260-10H) after subjecting them to standard cleaning (SC-1,SC-2, SC-1). The heat treatment is performed on the condition that at1150° C., for 4 hours, and in argon atmosphere (Ar 100%). After thewafer was unloaded, it was subjected to the heat treatment using a RTAapparatus (Steag MicroTech International, SHS-2800 type), at 1200° C.,for 30 seconds in a mixed gas atmosphere of nitrogen and oxygen. Then,in order to elicit oxide precipitates, it was subjected to the heattreatment at 800° C. for 4 hours and at 1000° C. for 16 hours innitrogen atmosphere, and a density of the oxide precipitates in a bulkpart and a width of the DZ layer were measured.

For comparison, there were also evaluated the wafers that subjected onlyto the heat treatment using a horizontal-type batch processing furnaceof the above-mentioned heat treatments (Comparative Example 1: the waferA, the Comparative Example 3: the wafer B), and the wafers that notsubjected to any of the heat treatments (Comparative Example 2: thewafer A, Comparative Example 4: the wafer B).

A density of oxide precipitates was measured according to the OPP(Optical Precipitate Profiler) method. A width of the DZ layer wasmeasured by conducting an angle-polishing from the wafer surface,subjecting the angle-polished face to preferential etching (Seccoetching), and making an observation with an optical microscope.Therefore, a measured width of the DZ layer is not a value which shows avoid-free region.

The conditions of the heat treatment described above and the resultswere shown in Table 1.

TABLE 1 Item Density of Kind Heat oxide Width of DZ Example of Treatmentprecipitate layer No. wafer Step (counts/cm³) (μm) Example 1 AHorizontal-type 5.1 × 10⁹ 35 furnace + RTA Comparative A Onlyhorizontal- 6.3 × 10⁸ 65 Example 1 type furnace Comparative A Nothing1.0 × 10⁷ Measurement Example 2 impossible Example 2 B Horizontal-type1.0 × 10⁸ Measurement furnace + RTA impossible Comparative B Onlyhorizontal- 1.0 × 10⁷ Measurement Example 3 type furnace impossibleComparative B Nothing 1.0 × 10⁷ Measurement Example 4 impossible Note:Wafer A: nitrogen concentration: 1.0 × 10¹³ atoms/cm³, oxygenconcentration: 15 ppma. Wafer B: Nitrogen concentration: Non doping,oxygen concentration: 15 ppma.

It has been turned out from these results that in the case that thewafer A sliced from the crystal which is doped with nitrogen issubjected to the heat treatment, there exist more oxide precipitates ascompared with the wafer B which is not doped with nitrogen, and thatoxide precipitates are increased by further subjecting to the RTAtreatment.

In addition, 65 μm of the DZ layer of oxide precipitates existed in thewafer A (Comparative Example 1) which was subjected only to the heattreatment using a horizontal-type batch processing furnace, whereas 35μm of the DZ layer existed in the wafer A (Example 1) which wassubjected to RTA treatment additionally. This shows that a width of theDZ layer got narrow, as a result that oxygen precipitation was promotedby the RTA treatment. It is likely to be thought that it is adisadvantageous effect apparently that a width of the DZ layer becamenarrow. However, since the width demanded as a part to be a deviceactive region is at most about 10 μm, 35 μm of the DZ layers issufficient. On the contrary, since the density of oxide precipitates isincreased one digit, the gettering ability is improved, and such aneffect is more important. On the other hand, a width of the DZ layer ofthe wafer B which is not doped with nitrogen (Example 2, ComparativeExamples 3 and 4) was not able to be measured clearly, since a densityof oxide precipitates was low. Similarly, a width of the DZ layer of thewafer A (Comparative Example 2) which was not subjected to the heattreatment steps could not been measured.

Furthermore, the crystal defects in the bulk part of the nitrogen dopedwafer A were observed with TEM (a transmission electron microscope), andthereby it was confirmed that dislocations were generated by the RTAtreatment. These dislocations act effectively for gettering.

EXAMPLE 3, EXAMPLE 4

In order to confirm the effect on the void-free region of the RTA heattreatment in addition to the heat treatment with a resistance-heatingtype heat treatment furnace, the following two kinds of CZ siliconwafers (C, D) were produced, and the following experiments wereconducted using them.

Example 3: Wafer C: a diameter of 150 mm, a conductivity type of p type,crystal orientation of <100>, a resistivity of 10 Ω·cm, nitrogenconcentration of 1.0×10¹³ number/cm³ (a calculated value), oxygenconcentration of 13 ppma (JEIDA).

Example 4: Wafer D: a diameter of 150 mm, a conductivity type of p type,crystal orientation of <100>, a resistivity of 10 Ω·cm, nitrogenconcentration of 1.0×10¹³ number/cm³ (a calculated value), oxygenconcentration of 15 ppma (JEIDA).

First, these wafers were subjected to heat treatment with thehorizontal-type batch processing furnace (manufactured by Tokyo ElectronLimited, UL-260-10H) after subjecting them to standard cleaning (SC-1,SC-2, SC-1). The heat treatment was performed on the condition that at1200° C., for one hour, in argon atmosphere (Ar 100%). After the waferwas unloaded, it was subjected to the heat treatment using a RTAapparatus (Steag MicroTech International, SHS-2800 type), at 1200° C.,for 30 seconds (in a mixed gas atmosphere of nitrogen and oxygen). Forcomparison, the wafers C (Comparative Example 5) and the wafers D(Comparative Example 6) which are not subjected to the RTA heattreatment (subjected only to the heat treatment at 1200° C., for onehour, in Ar) were also produced.

Then, the wafers thus produced were polished to the predetermined depthfrom a surface, and oxide dielectric breakdown voltage characteristics[TZDB (Time Zero Dielectric Breakdown) good chip yield] in each depthwas measured. The TZDB good chip yield has a good correlation with avoid defect (COP). It is known that an good chip yield is reduced ifthere are many void defects.

In measurement of the TZDB good chip yield, the good chip yield wascalculated by forming a 25 nm of thermal oxide film on a surface of thewafer, forming further a polysilicon electrode which was doped withphosphorus (P) (electrode area of 8 mm²) thereon, and determing thoseshowing dielectric breakdown electric field of 8 MV/cm or more at acurrent density in decision of 1 mA/cm² as good chips at 100 points in aplane of the wafer. The results were shown in FIG. 2.

As shown in FIG. 2, it has been turned out that, in both wafers havinginitial oxygen concentration of 13 ppma and 15 ppma, the depth at whicha TZDB good chip yield is reduced becomes deeper, namely the void-freeregion spreads more deeply, by being subjected to the RTA heattreatment.

Although it is not known exactly why a void-free region spreads by beingsubjected to the RTA heat treatment, it is concluded that by adding theRTA heat treatment to the heat treatment with a resistance-heating typeheat treatment furnace, the void-free region is expanded, and moreover,increase of a density of oxide precipitates and generation of defectssuch as dislocation are promoted from the results of Example 1 andExample 2. Therefore, it has been found out that improvement in aquality of the DZ layer and improvement in gettering ability can beachieved simultaneously.

The present invention is not limited to the above-described embodiment.The above-described embodiment is a mere example, and those having thesubstantially same structure as that described in the appended claimsand providing the similar action and effects are included in the scopeof the present invention.

For example, in the above-described embodiment, it is exemplified thatthe silicon single crystal wafer having a diameter of 6 inches wassubjected to the heat treatment. However, the present invention is notlimited thereto, and can be applied to a silicon single crystal waferhaving a diameter of 8 to 16 inches, or more.

Furthermore, the present invention can also be applied to a siliconsingle crystal wafer, irrespective of a method by which the crystal isproduced, whether it is CZ method, MCZ method or any other methods.

What is claimed is:
 1. A method for producing a silicon single crystalwafer which contains oxygen induced defects by subjecting a siliconsingle crystal wafer containing interstitial oxygen to a heat treatmentwherein the heat treatment includes at least a step of performing a heattreatment in a hydrogen atmosphere, an inert gas atmosphere or anatmosphere of a mixture of these gases using a resistance-heating heattreatment furnace and a step of performing a heat treatment using arapid heating and rapid cooling apparatus.
 2. The method for producing asilicon single crystal wafer according to claim 1 wherein the heattreatment using the resistance-heating heat treatment furnace isperformed at 1000 to 1300° C. for 10 to 300 minutes, and the heattreatment using the rapid heating and rapid cooling apparatus isperformed at 1000 to 1350° C. for 1 to 300 seconds.
 3. The method forproducing a silicon single crystal wafer according to claim 2 wherein asilicon single crystal wafer which is doped with nitrogen at aconcentration in the range of 1×10¹⁰ to 5×10¹⁵ number/cm³ is used as thesilicon single crystal wafer to be subjected to the heat treatment. 4.The method for producing a silicon single crystal wafer according toclaim 3 wherein a silicon single crystal wafer which is doped withcarbon at a concentration in the range of 0.1 to 5 ppma is used as thesilicon single crystal wafer to be subjected to the heat treatment.
 5. Asilicon single crystal wafer produced by the method for producing asilicon single crystal wafer according to claim
 4. 6. A silicon singlecrystal wafer produced by the method for producing a silicon singlecrystal wafer according to claim
 3. 7. The method for producing asilicon single crystal wafer according to claim 2 wherein a siliconsingle crystal wafer which is doped with carbon at a concentration inthe range of 0.1 to 5 ppma is used as the silicon single crystal waferto be subjected to the heat treatment.
 8. A silicon single crystal waferproduced by the method for producing a silicon single crystal waferaccording to claim
 7. 9. A silicon single crystal wafer produced by themethod for producing a silicon single crystal wafer according to claim2.
 10. The method for producing a silicon single crystal wafer accordingto claim 1 wherein a silicon single crystal wafer which is doped withnitrogen at a concentration in the range of 1×10¹⁰ to 5×10¹⁵ number/cm³is used as the silicon single crystal wafer to be subjected to the heattreatment.
 11. The method for producing a silicon single crystal waferaccording to claim 10 wherein a silicon single crystal wafer which isdoped with carbon at a concentration in the range of 0.1 to 5 ppma isused as the silicon single crystal wafer to be subjected to the heattreatment.
 12. A silicon single crystal wafer produced by the method forproducing a silicon single crystal wafer according to claim
 11. 13. Asilicon single crystal wafer produced by the method for producing asilicon single crystal wafer according to claim
 10. 14. The method forproducing a silicon single crystal wafer according to claim 1 wherein asilicon single crystal wafer which is doped with carbon at aconcentration in the range of 0.1 to 5 ppma is used as the siliconsingle crystal wafer to be subjected to the heat treatment.
 15. Asilicon single crystal wafer produced by the method for producing asilicon single crystal wafer according to claim
 14. 16. A silicon singlecrystal wafer produced by the method for producing a silicon singlecrystal wafer according to claim 1.